A well is a three-dimensional region or portion of a semiconductor substrate, having majority charge carriers of a different conductivity type (for example P-type) in comparison to the majority charge carriers of the surrounding portion of the substrate around the well (for example N-type). As a result, blocking or non-conductive PN-junctions will be formed along the peripheral edges or boundaries of the well, in connection with a suitable electrical reverse-biasing thereof, whereby these PN-junctions effectively electrically isolate the interior of the well from the surroundings thereof.
Various semiconductor devices include different types of trench structures in a semiconductor substrate. For example, such trenches are used for electrical isolation of so-called component boxes, pockets or tubs in the depth and/or on the surface of the semiconductor substrate. As a further example, such trenches are used for the three-dimensional formation or configuring of electrically active regions such as a trench capacitor or a transistor drift zone within the semiconductor substrate. Generally, deep trenches are used to achieve electrical isolation in the depth direction, while shallow trenches are preferred for achieving the three-dimensional formation or configuration of electrically active regions and also for electrical isolation purposes on the surface of the substrate. Deep trenches and shallow trenches are differentiated from one another by the aspect ratio of the depth relative to the width thereof. Deep trenches have an aspect ratio of greater than one and shallow trenches have an aspect ratio of less than or equal to one. In other words, deep trenches are deeper than they are wide, while shallow trenches are as wide as or wider than they are deep.
It is generally known in the art to form wells and trenches as mentioned above, as well as various active regions within a semiconductor substrate to form a semiconductor device. Examples of such active regions include individual transistors that are integrated into the same common substrate. The individual active regions are separated from one another by field areas or field regions, so that the surface of the semiconductor substrate can be divided into active regions and field regions that are complementary to each other.
A device fabrication method incorporating the above features is known, for the special case of fabricating a DMOS-transistor as a semiconductor element, from the German Laying-Open Publication DE 101 31 705 A1, as well as the counterpart U.S. Pat. No. 6,780,713 (Bromberger et al.), the entire disclosure of which is incorporated herein by reference.
The above mentioned field regions are provided with insulating or isolating structures in order to avoid an undesired drift of charge carriers, i.e. electrons or holes, between the respective active regions. In integrated circuits based on silicon technology, it is known to isolate respective active regions on the surface of the device or circuit from each other by means of an insulation structure consisting of a silicon oxide, generally called a field oxide.
On the other hand, active regions are isolated from one another in the depth of the structure of the integrated circuit by means of the deep trenches mentioned above, or alternatively or additionally by well regions or wells used for the lateral isolation. Such wells are typically produced through implantation of a dopant followed by thermally supported diffusion of the dopant into the semiconductor substrate. Since the diffusion is generally not directional, i.e. does not proceed along a preferred direction, the diffusion typically occurs both in the depth direction as well as in the width or lateral direction. Thus, the lateral spreading of the wells will become ever greater as the wells are to be diffused or driven deeper into the semiconductor substrate such as silicon, by a high temperature well drive step. In other words, as the dopant is diffused deeper into the substrate it necessarily also spreads wider in the lateral direction. As a result, the mutual influence or interference of adjacent wells or adjacent regions due to out-diffusion will also increase. In this regard, the term “out-diffusion” refers to a reduction of a net concentration of the dopants along the peripheral edge or boundary of a well due to a lateral diffusion of dopants out of an oppositely doped adjacent or neighboring well. Thus, the net dopant concentration of the intended dopant type of a given well falls off or diminishes toward the lateral boundaries thereof adjacent to a neighboring well of opposite dopant polarity.
In the fabrication method known from the above mentioned German Patent Laying-Open Publication DE 101 31 705 A1, respective well regions are defined through an implantation of dopants into areas near the surface of the substrate, followed by a complete in-diffusion, i.e. diffusion of the dopant into the substrate volume by a thermal drive-in step, before the further subsequent formation of deep trenches that will define component boxes isolated from each other within the substrate. Still further in the known method according to the German Publication mentioned above, another trench structure is formed by a Shallow Trench Isolation (STI) etching process, and then a separate doping of the boundaries (walls and floor) of the trench is carried out to form a drift zone of the DMOS-transistor.
The above mentioned conventional process of defining the wells before forming trenches can unfortunately suffer the effects of the above discussed out-diffusion, especially if high dopant concentrations and/or deep diffusion penetration depths are to be achieved. In order to avoid or prevent such undesired influences of out-diffusion along the respective boundaries of neighboring well regions of opposite conductivity type, the spacing distance between electrically active regions with different well dopings must be selected sufficiently large so that the respective dopant species do not out-diffuse and thus counteract the intended doping in the neighboring well region. However, such a large spacing distance between differently doped well regions undesirably limits the packing density of device structures per surface area. In other words, the lateral spacing of the well regions from each other to avoid the undesirable influences of out-diffusion mutually between neighboring wells requires a corresponding minimum lateral width of the total device structure, which necessarily limits the possible size-reduction or miniaturization of the device.